Not Your Mother's SoC: Combining IP Reuse with HLS in an Integrated SoC Design and Verification Flow
One of the great productivity boosters in SoC design today is the use of High-Level Synthesis (HLS), which has equally beneficial impacts in both the design and verification flows. HLS increases productivity and reduces risk by allowing users to raise the level of design abstraction, to explore a greater range of "what-if" architectural scenarios, and to more fully analyze and verify the high-level functionality of the design before committing to a final implementation.
Another great productivity booster is the reuse of internally-generated and third-party-provided silicon intellectual property (IP). The use of IP has been growing steadily over the years. Depending on the design in question, IP blocks may account for anywhere up to 90% of the design.
But can an IP reuse methodology work within a high-level synthesis flow? Our virtual conference will explore how the industry's top design and verifications teams are approaching the problem.
Who Will Participate
- IP Developers
- System Architects
- DSP Designers
- Hardware Design Engineers
- Embedded Software and Firmware Developers
- Verification Engineers
- Project Managers
About the Technical Program
The program will include a keynote address, a combination of sponsored and editorially selected panelists, and one or more sponsored webinars.
Attend the 2010 Archived SoC Virtual Conference