Program Schedule
 
 

Content Overview

Multicore: Making Multicore Work for You

Multicore processors are forcing a rethink of hardware design as well as programming practices. Do you want multiple identical CPU cores or a mix of difference CPU cores for each task? What's the best way to harness all this horsepower? And do multicore chips really reduce power consumption or are they just performance overkill? Whatever the answers, multicore isn't going away. It's a design reality. Whether you're an engineer, a manager, or a programmer, a few intensive hours spent here will pay off now and down the road.

Tracks

Panel Discussion:
High-End Multicore Chips: How Much Performance Can You Get?
From Intel and AMD to Tilera and Applied Micro, many companies are making high-end microprocessor chips with as many as 100 CPU cores. How can you harness this power, and what would it take to make it work for you?

Panel Discussion:
Simple Matter of Programming: Software Architecture for Multicore
The first thing to think about (or worry about) with multicore systems is how you're going to architect, or segregate, your code. Do you use multiple operating systems or one? Run multiple threads on different cores? Use one core to debug the others? And what role does your compiler play? In this session we dissect the software, operating system, and EDA landscape as it applies to multicore programming, picking up the best habits and practices from our panel of experts.

Panel Discussion:
Highly Integrated Multicore Systems: Balancing Performance, Power, Price, and Built-in Intelligence
Multicore systems can span the range from low-end and low-cost all the way up to high-performance, highly specialized application-specific designs. The hardware and the software come in many configurations, too: symmetric (SMP), asymmetric (AMP), offload engines, cores dedicated to peripheral I/O, encryption, networking, graphics, power-management, and more. See and hear how low-cost, highly integrated multicore solutions can simplify embedded design without adding cost or busting the power budget. This session helps designers and managers sort through the many options, locating the most practical and cost-effective approaches.


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photo of Yale PattKeynote:

Multicore, Meganonsense, and the Future, if We Get It Right

Presenter: Yale Patt, Professor of Electrical and Computer Engineering, and Ernest Cockrell, Jr. Centennial Chair in Engineering, The University of Texas at Austin


Click panels to expand/contract
Keynote Address
Panel Discussion: 12:30 pm EST to 1:30 pm EST
Multicore, Meganonsense, and the Future, if We Get It Right

Presenter: Yale Patt, Professor of Electrical and Computer Engineering, and Ernest Cockrell, Jr. Centennial Chair in Engineering, The University of Texas at Austin

Computer architecture is all about tradeoffs. That is as true with multicore today as it was with the first pipeline several decades ago. Homogeneous vs heterogeneous, GPU vs. CPU, one interface vs two interfaces -- all have implications. In this talk I'll briefly show you how we got to multicore, deflate some of the silliness that has come into play -- I call it meganonsense -- and then get into my expectations for future multicore chips and what engineers will need to do to take full advantage of them.

BIO
Patt directs the research of eight PhD students and regularly teaches the very demanding, required Introduction to Computing course to more than 400 freshmen and his advanced graduate course in Microarchitecture to those planning careers as cutting-edge computer architects. Some of his research ideas have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students.

The textbook for his unconventional approach, "Introduction to Computing Systems: from bits and gates to C and beyond," written with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide. He has received many of the highest honors in the field for both his research and teaching, including the 1996 IEEE/ACM Eckert-Mauchly Award, and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award. He is a Fellow of both the IEEE and ACM. More detail is available on his web site.

High-End Multicore Chips: How Much Performance Can You Get?

Panel Discussion: 11:15 am EST to 12:15 pm EST

Moderator: Jim Turley, Principal Analyst, Silicon Insider

Panelists:
▸ Jim St. Leger, technology marketing manager, Embedded and Communications Group, Intel
▸ Ihab Bishara, Director of server solutions, Tilera
▸ Darren Jones, Engineering Director, Microprocessor Development, MIPS Technologies, Inc.
▸ Navanee Sundaramoorthy, Product Manager, Embedded Processing Platforms, Xilinx, Inc.

From Intel and AMD to Tilera and Applied Micro, many companies are making high-end microprocessor chips with as many as 100 CPU cores. How can you harness this power, and what would it take to make it work for you? In this hour we examine a number of high-end multicore chips and weigh the pros and cons of using them in consumer, computer, and communications applications. What are the hardware tradeoffs and how do these chips affect your programming environment? And how can massively multicore chips paradoxically reduce power consumption? We talk to the experts, and you're invited.

Dodging the 11th-Hour Train Wreck
Scheduled Chat: 2:00 pm EST to 3:00 pm EST

Moderator: Jim Turley, Principal Analyst, Silicon Insider

Selecting chips and partitioning hardware and for multicore systems is a new experience for most engineers and programmers. There always seems to be that "Oh, no!" moment, when the wheels fall off the wagon just when you're under the gun to get the project finished. Help your fellow engineers avoid this terror by sharing your experience and problems in multicore hardware in this on-line interactive chat hosted by Jim Turley. Raise your warning flag, tell your story, or offer a solution.

Simple Matter of Programming: Software Architecture for Multicore
Panel Discussion: 3:00 pm EST to 4:00 pm EST

Moderator: Rick Merritt, Editor at Large, EE Times
Panelists:
▸ Tasneem G. Brutch, Ph.D., Sr. Staff Engineer, Computer Science Lab, Samsung Information Systems America
▸ Bill Graham, Product Marketing Manager, VxWorks, Wind River
▸ Surender Kumar, Software Specialist, Nokia Siemens Networks
▸ Robert Mueller-Albrecht, Staff Software Engineer / Technical Consulting Engineer, Intel

The first thing to think about (or worry about) with multicore systems is how you're going to architect, or segregate, your code. Do you use multiple operating systems or one? Run multiple threads on different cores? Use one core to debug the others? And what role does your compiler play? In this session we dissect the software, operating system, and EDA landscape as it applies to multicore programming, picking up the best habits and practices from our panel of experts.

Multicore Software: Good and Bad

Moderator: Rick Merritt, Editor at Large, EE Times

What has multicore done for your career, and had it been a good thing or a bad thing? It opens up new avenues of development, and it certainly encourages learning new skills, but has it made your job or your industry better? Jump in and participate with like-minded attendees and your moderator, Rick Merritt. This scheduled group chat will take place in the Communications Center.

Programming methods and software development tools...

Sponsored Chat: Programming methods and software development tools for adopting multi-core technology

Panel Discussion: 4:00 pm EST to 4:30 pm EST

Moderators:
▸ Lori Matassa, Platform Software Architect, Intel Embedded and Communications Group
▸ Robert Mueller-Albrecht, Staff Software Engineer / Technical Consulting Engineer

The software design and effort involved to adopt multi-core technology will vary depending on the starting point of your software and project requirements. This chat will focus on multi-core software design including asymmetric and symmetric multiprocessing decisions and choices. In addition, multi-core tools will be discussed for programming and debugging multi-core systems.

Highly Integrated Multicore Systems...

Panel Discussion: Highly Integrated Multicore Systems: Balancing Performance, Power, Price, and Built-in Intelligence
5:00 pm EST to 6:00 pm EST

Moderator: Jim Turley, Principal Analyst, Silicon Insider

Panelists:
▸ Mark Guinther, Product Line Manager for Networking, Wind River
▸ Grant Martin, Chief Scientist, Tensilica
▸ Bob Beachler, Vice President, Marketing, Operations, Systems Design, Stretch Inc.
▸ David Stewart, CEO, CriticalBlue

Multicore systems can span the range from low-end and low-cost all the way up to high-performance, highly specialized application-specific designs. The hardware and the software come in many configurations, too: symmetric (SMP), asymmetric (AMP), offload engines, cores dedicated to peripheral I/O, encryption, networking, graphics, power-management, and more. See and hear how low-cost, highly integrated multicore solutions can simplify embedded design without adding cost or busting the power budget. This session helps designers and managers sort through the many options, locating the most practical and cost-effective approaches.

 

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