Hardware/software design on ARM processors
Benchmarking an ARM-based SoC using Dhrystone: A VFT perspective
Building small footprint embedded GUIs for ARM Cortex-M designs using Java
ARM-based Android hardware-software design using virtual prototypes - Part 1: Why virtualize?
Improve Cortex M4 MCU interrupt responses with an intelligent Peripheral Event System
The cornucopia of technology and product news that emerged from the 2012 ARM TechCon last week is testament to the powerful attraction of the architecture to both embedded hardware and software developers. Some of the late-breaking news and product stories that caught my eye include IS2T's 1.5 KB RAM JVM for Cortex M MCUs, Cadence's 14 nm FinFET ARM test chip, and the ARM emulation of the X86 from Elbrus.
The ARM architecture is the focus of so much attention for two reasons. First, ARM Ltd. and its licensees continue to push the limits of where the architecture can be used. Second, they continue to develop the necessary techniques and tools to use them with exactly the right mix of power versus performance and flexibility versus usability. Four new Editor's Top Picks that illustrate these trends are:
"Building small footprint GUIs for ARM Cortex-M using Java" details how to use new small footprint Java implementations to build GUIs for ARM designs more compact than using either C or C++.
"ARM-based Android hardware-software design using virtual prototypes" is a three-part series describing how to use of high-level virtual prototyping for integrating hardware and software development.
"Improve Cortex M4 interrupts with an intelligent Peripheral Event System" demonstrates how Atmel's 32-bit Cortex M4 MCU interrupt response times were improved by means of an intelligent Peripheral Event System previously used on its 8- and 16-bit MCUs.
"Benchmarking an ARM-based SoC using Dhrystone," describes a self-checking, result-signaling test-pattern version of the popular Dhrystone benchmark that provides performance numbers from an ARM-based SoC. You can compare those numbers to those predicted by architectural analysis and RTL simulations.
Also included are recent ARM-related design and development how-to articles, technical papers, webinars, conference papers, and journal articles, as well as commentary and analysis blogs. Of the latter, I recommend re-reading "Is 8-bits dead?", Jack Ganssle's recent "pre-mortem" analysis of the future of 8-bit MCUs in the world of 32-bit ARM MCUs. Do his arguments in favor of a continued future for non-ARM MCUs still hold true? Or are Michael Barr's arguments in "Trends in embedded software design," favoring the 32-bit ARM more realistic?
Editor's Note: Planning is underway for the program of events and classes at the Embedded Systems Conference at DESIGN West in April 2013. If you are interested in teaching a class at the conference, submit an abstract by November 9. We are also looking for ideas for the keynote, so go to "Design your own keynote," and leave your suggestions about topics and speakers.
Power aware verification of ARM-based designs
How to deal with the challenges of power aware verification in SoCs and use IEEE 1801-2009 Unified Power Format to define power management architecture for verifying a power-managed ARM-based design.
Implement an MP3 audio decoder with the ARM Neon Multimedia extensions
How the ARM Cortex-A8's NEON multimedia instruction extensions can be used to implement the MP3 audio algorithms on Freescale's i.MX51 mobile media processor platform.
Get control of ARM system cache coherency with ACE verification
In this Product How-Two article, the Cadence authors describe how to use the company's Verification IP solutions framework to implement ARM's AMBA 4 Coherency Extensions (ACE) in embedded SoCs
Decompiling the ARM architecture code
At UBM TechInsights we are often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. Our example algorithm is based on the ARM architecture.
Basics of porting C-code to and between ARM CPUs: ARM7TDMI and Cortex-M0
In this three part series, Joseph Yiu, author of "The definitive guide to the ARM Cortex-M0," provides some basic guidelines for porting your code base from other 8/16 bit MCUs to ARM and between various ARM processors. Part 1: ARM 7TDMI and Cortex-M0.
Building Bare-Metal ARM Systems with GNU: Part 1 - Getting Started
In this first part in an on-going series of ten articles, Miro Samek of Quantum Leaps details developing apps on the ARM processor using QNU, complete with source code in C and C++. First up, laying the ground work
Energy efficient C code for ARM devices
Here is an overview of some of the techniques for optimizing C-code for use on the ARM architecture.
Reliable programming in ARM assembly language
Sometimes it's necessary to use both assembly and high-level programming languages when working in the ARM architecture. This paper from ARM TechCon explains why and how.
IS2T's JVM boots in 2 ms at 120 MHz, uses less than 1.5 KB RAM
IS2T today announced MicroEJ, which the company claims is the industry's first Java platform to support the development and integration of Java-based functionality for low-cost, memory-constrained, C and C++ applications running on Cortex M-based microcontrollers.
New versions of Mentor Sourcery tools ease development of multicore Linux-based embedded systems
The newest generation of Mentor Graphics' Embedded Sourcery CodeBench and Sourcery Analyzer products accelerates system debugging, including multiple Linux applications concurrently
ThreadX RTOS supports ARM and TI DSP processors on Critical Link's MityDSP-L138F
Express Logic Inc.'s ThreadX RTOS now supports Critical Link's MityDSP-L138 board. The MityDSP-L138F system-on-module (SoM) combines a TI C674x floating point DSP, an ARM9 processor, and an optional FPGA.
TRACE32 debuggers now support ARMv8 architecture
The ARMv8 Embedded Trace Macrocell (Ev4) from Lauterbach provides non-intrusive program-flow trace and data trace capabilities for any of the ARMv8 architecture-based processors.
Next-gen SmartFusion2 SoC FPGA boasts breakthru security, reliability, and low power
Microsemi Corporation's SmartFusion2 system-on-chip (SoC) field programmable gate array (FPGA) family is designed to address fundamental requirements for advanced security, high reliability, and low power.
ITTIA DB SQL enables accelerated development in ARM-based systems
ITTIA's embedded database is now available for the ARM architecture.
Cortex-M based MCUS use power profiles to optimize performance
With its latest Cortex-based LPC1100L and LPC1300L microcontrollers NXP Semiconductors is aiming to raise the benchmarks in 32-bit active power consumption.
IAR adds ARM compiler optimizations to Embedded Workbench
Version 6.5 of the IAR Embedded Workbench for ARM version 6.50, includes enhancements to the optimization technology in its C/C++ Compiler.
Cadence tapes out 14nm ARM test chip with IBM FinFETs
Effort is part of Cadence and IBM cooperation on SoC process design at 14 nanometers and beyond that combine performance with reductions in power consumption.
Renesas adds ARM processors to its MCU mix
Renesas expands its RX microcontroller line to span from 8 kilobytes to 8
megabytes of scalable embedded flash.
ARM's 64-bit V8 scheduled for 16-nm FinFET CMOS
TSMC is planning within the next 12 months to use ARM Ltd.'s 64-bit V8 processor as the test vehicle for its 16 nm CMOS process.
X86 emulation coming to ARM processors
While initially most useful in ARM's efforts in competing with Intel in servers, new x86 emulation software from Elbrus could also offer new choices to embedded developers.
LSI's first ARM net processor links 16 cores
LSI Corp. has successfully developed an ARM-based network processor SoC capable of linking up to 16 cores.