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Tech Focus
Managing interrupts for low latency response time
Improve Cortex M4 MCU interrupt responses with an Intelligent Peripheral Event System
Interrupts short and simple: Part 1 - Good programming practices
Introduction to Interrupt Debugging
Introduction to Interrupts
Editor's Note
No matter whether it is design based on an 8-bit or 16-bit MCU, a 32-bit ARM or Atom, or a multicore SoC, one common challenge faces the embedded system developer: as a system's functional requirements and the size of the software grow, it becomes more difficult to ensure that time-critical operations are performed with as little interruption as possible.
The problems can be addressed by either using a faster processor - which is not realistic in many resource-constrained designs - or more commonly execute them in a prioritized manner, through the use of a variety of interrupt management and scheduling schemes.
But this is not achieved easily, as the designer is faced with a variety of roadblocks. Because software cannot predict when interrupts will occur and thus pause execution of other operations, it is no surprise that without a considerable degree of effort, the result is the inability to perform system and application critical operations within the design constraints originally defined.
Collected here are a range of design articles, white papers, webinars and columns by Jack Ganssle, Jack Crenshaw and Dan Saks to help you sort through the problems and their possible solutions. In addition to "Improve Cortex M4 MCU interrupt responses with an Intelligent Peripheral Event System," by Andreas Eieland, and Espen Krangnes, and "Interrupts short and simple," a three part series of tutorials by Priyadeep Kaur, my Editor's Top Picks are:
Optimized interrupt handling
Testing the Interrupt Priority Levels of a Microprocessor
Introduction to interrupt debugging
Editor's Note: Planning is currently underway for the program of events and classes at the Spring ESC DESIGN West in April, 2013. If there is a topic you think is important to communicate to your fellow embedded systems developers, submit an abstract, right away. Submission deadline is Nov. 2, the end of this week. We are also looking for ideas for the keynote events, so go to "Design your own keynote," and leave your suggestions about topics and speakers.
Development
Improve Cortex M4 MCU interrupt responses with an Intelligent Peripheral Event System
In this Product How-To design article, Atmel's Andreas Eilan and Espen Krangnes describe how they improved interrupt response times and reduced device driver development time for developers of applications using the company's Cortex M4 MCU based implementation with the use of an intelligent Peripheral Even System previously used on its 8- and 16-bit MCUs
Interrupts short and simple: Part 1 - Good programming practices
In this first part in a series on the appropriate use of interrupts in embedded systems design, Priyadeep Kaur of Cypress Semiconductor starts with general guidelines and good practices that should be followed.
Interrupts short & simple: Part 2 - Variables, buffers & latencies
In this second part in an on-going series on the appropriate use of interrupts in a variety of embedded systems design environments, Priyadeep Kaur discusses ISRs, global/local variables, data buffers, shared memory and the interrupt timing latencies.
Interrupts short and simple: Part 3 - More interrupt handling tips
In this third part in a series on the appropriate use of interrupts in embedded systems design, Priyadeep Kaur discusses right and wrong practices while using buffers with ISRs.
Reduce RTOS latency in interrupt-intensive apps
Here is a way to bypass the RTOS in latency-sensitive interrupt situations. The use of a hybrid interrupt handling technique may reduce or eliminate the latency introduced by the RTOS in many embedded designs
Minimize your ISR overhead
With all the automated tools available today, it's easy to lose track of the overhead that such tools are introducing.
Interrupts in C++
An ideal C++ device driver would be a class containing, among other things, the ISR as a member function. But this is harder to achieve than many C programmers assume.
Interrupt Management Under Linux: Using the Interrupt Controller API
Bill Gatliff provides a walkthrough of the portions of the Linux kernel that manage interrupts and describes how Linux interacts with interrupt controllers and how to adapt code for custom hardware.
Building Bare-Metal ARM Systems with GNU: Part 1 - Getting Started
In this first part in an on-going series of ten articles, Miro Samek of Quantum Leaps details developing apps on the ARM processor using QNU, complete with source code in C and C++. First up, laying the ground work
Back to the basics: Doing Hardware Counter/Timer design using High School Science
Using the same unit-conversion techniques and dimensional analysis techniques learned in high school, Zane Purvis takes non-engineers and newcomers to embedded design step-by-step through the configuration of a counter/timer.
Products
Tektronix introduces one-stop PCIe 3.0 testing and debug
Tektronix now offers designers a single destination for PCI Express 3.0 testing with its automated transmitter (Tx) and receiver (Rx) compliance and debug testing solution for the PCI Express 3.0 standard.
Atmel combines maXTouch controllers and maXFusion technology on a single chip
Atmel Corporation has announced new microcontroller-based solutions that integrate touch and sensor hub functionality for a variety of mobile devices including smartphones, tablets, Ultrabooks and convertible PCs.
Telit LTE cellular module delivers 100Mbps download with fallback to HSPA+/GSM/GPRS
The LE920 LTE cellular module from Telit Wireless Solutions features a new 920 form factor measuring 34x40x2.8mm on a 198-pad LGA automotive-grade package.
Industry
FRAM helps TI cut power for Wolverine MSP430 platform
Wolverine is the moniker chosen by Texas Instruments for an ultra-low-power MSP430 microcontroller platform launched here which provides 360 nA real-time clock mode - more than doubling battery life - and less than 100 μA/MHz active power consumption.
LDRA tool suite supports integration with VisualDSP++
LDRA has integrated its tools suite with the Analog Devices VisualDSP++ (VDSP++) software development environment. The tool suite provides automated software testing and verification across all stages of software development.
Cortex-M based MCUS use power profiles to optimize performance
With its latest Cortex-based LPC1100L and LPC1300L microcontrollers NXP Semiconductors is aiming to raise the benchmarks in 32-bit active power consumption.
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