ARM TechCon™ 2012

Sponsored Sessions

Sponsored Sessions take place October 25-27, 2011 and are open to ALL attendees. The sessions grant you in-depth hands-on solutions to specific challenges. These aren't product pitches or cleverly disguised marketing ploys; this is the real stuff that engineers want and need to get their jobs done.

Select the sessions you would like to attend here!

Space in the sessions is first-come, first-serve. These sessions can also be viewed in Schedule Builder.

Tuesday, October 25, 2011
	Progressive Verification of a Cortex A15 Based SoC Using Hardware Emulation Time: 11:00am - 11:50am Location: Ballroom C Speaker: Jim Kenney, Marketing Director, Mentor Graphics With the advent of UVM/OVM transaction-based testbenches and accelerated master/slave transactors for AXI and APB, it’s now straight forward to apply hardware emulation to the complete verification flow from block-level simulation acceleration to full chip HW/SW co-verification including virtual peripherals. This presentation walks through the verification flow beginning with block-level validation of a GPU with AXI interfaced source and destination memories. A virtual graphics analysis tool is added to augment testbench inspection of the image memory. The Cortex A15 including the graphics device driver is introduced along with advanced firmware debug techniques. The AXI accelerated transactor, virtual graphics analysis, and PCIe rate adaptor are also detailed. Key Takeaways: Simulation acceleration of OVM block-level tests; Application of Virtual Peripherals to block level and full SoC verification; Emulation of an SoC with embedded SW and peripheral devices; Advanced software debug methods for Cortex A-15 multi-core SoCs.
	TSMC Technology, OIP Eco-system and ARM Time: 11:00am - 11:50am Location: Room 202 Speaker: Dan Kochpatcharin, Deputy Director, TSMC TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The presentation will cover TSMC Technology roadmap from 0.5um to the most leading node 20nm. In addition, TSMC has built an OIP design ecosystem with the objective of lowering the design barrier to improve product’s time-to-market. ARM-based processors lie at the heart of modern electronic devices in everywhere; The step up of ARM CPU performance alongside with its traditional low power consumption advantage, has enables a host of new electronic devices. The session will be of interested to designers who are planning or designing their next generation SOC. Key Takeaways: Roadmap to help designer with their next SOC planning.
	Optimized 28nm ARM Solution for Mobility Time: 12:00pm - 12:50pm Location: Ballroom C Speaker: Walter Ng, VP Design Enablement, GLOBALFOUNDRIES The Common Platform's 28nm SLP is the first 28nm process technology enabled by the ARM Artisan Physical IP. Designed for mobile SoC, the 28nm SLP features logic IP, Standard Cell, embedded memory compires, and IO's that have been optimized for the ARM Cortex-A9 processor. The Common Platform provides a comprehensive set of solutions with 28nm HKMG for low power and high performance applications. As the industry migrates to leading edge process technologies, designers are grappling with a myriad of challenges and trade-offs. To solve this, the Common Platform has been enabling designer by developing optimized IP that are supported across the companies in the Common Platform (GF, Samsung, and IBM). Key Takeaways: Common Platform is the first in industry with ARM based solutions in 28nm HKMG.
	Pushing the Limits of Performance Time: 12:00pm - 4:00pm Location: Room 202 Speakers: Masaitsu Nakajima, General Manager of Processor Core Technology, Panasonic Dr. Scott Thompson, CTO and senior vice president of technology, SuVolta, Inc. John Heinlein, VP of Marketing, ARM Physical IP Division John Ford, Director of Marketing, ARM Physical IP Division Wolfgang Helfricht, Advanced Products Marketing Director, ARM Physical IP Division ARM’s Physical IP division will host a ½ day session open to all attendees that provides an inside look at two compelling technology challenges SoC designers face today; low power GHz Cortex processor implementation and new advanced transistors at 20nm; FinFET, SOI and CMOS bulk planar. This is one session you won’t want to miss!
	Unified Flow for Mixed-Signal Design with Embedded Cortex-M0 Time: 2:10pm - 3:00pm Location: Ballroom C Speaker: Mladen Nizic, Engineering Director, Cadence Design Systems; Dominic Pajak, Embedded Segment Manager, ARM; Raviraj Mahatme, Platform Marketing Manager, ARM Cortex-M0 is often integrated with analog/mixed-signal IP including data converters, interfaces, RF-IC, sensors, and memory blocks. Designers must verify functionality for all modes of operation, optimize the floorplan, implement core and IP blocks, signoff on performance specs for timing, noise, and power, and effectively manage analog and/or digital ECOs. In this presentation, you will learn how to overcome these challenges by using a mixed-signal flow that integrates advanced analog and digital design capabilities and leverages the OpenAccess database. The flow supports a unified methodology that captures, communicates, and verifies design intent, abstracts AMS designs for scalability, and ensures continuous design convergence. Dominic Pajak, Embedded Segment Manager, ARM Dominic was a senior engineer in the ARM processor division, and later product manager for the ARM Cortex-M0 processor. Dominic holds a PhD in Computer Science and has been involved in the electronic engineering industry for over 10 years. Raviraj Mahatme, Platform Marketing Manager, ARM Raviraj is currently Platform Marketing Manager for physical IP at ARM in San Jose. His past experience was as a design engineer working on embedded memory. Raviraj holds a MS in Computer Engineering degree from NC State University and has been involved in the semiconductor industry for the last seven years. Key Takeaways: Integrating processor core with analog functionality offers flexibility and scalability, but realizing these benefits requires a better mixed-signal methodology to help designers meet multiple targets including area, performance, and power. The Cadence mixed-signal Solution, unified on The OpenAccess database, provides design intent management and effective abstraction, ensures fast design closure, and improves turnaround time, productivity, and silicon predictability.
	A High Performance Core Solution for 28/20nm ARM Cores Time: 3:10pm - 4:00pm Location: Ballroom C Speaker: Patrick Groeneveld, Ph.D., Chief Technologist, Magma Design Automation Designers of high performance cores such as ARM Cortex A15 need to maximize performance while minimizing power consumption and/or area. With an open, unified data model allowing full customization and leading-edge low-power dynamic and leakage technologies, working in harmony with advanced clock, placement and routing technology, the potential for a broadly differentiated ARM core becomes easy to converge on. In this session you will learn how a fully integrated design implementation system, shortens your overall design cycle time while maximizing quality of results on high-performance ARM cores. Key Takeaways: 1)Fully integrated solution for 28/20nm high performance ARM cores. 2) Big power savings with advanced clock gating. 3) Accurate memory characterization for reducing margins.
	Synopsys Session 1: Techniques for High Performance Cores using Synopsys Galaxy Platform—ARM® Cortex™-A15 Case Study Time: 4:10pm - 5:00pm Location: Ballroom C Speaker: Daniel Biset, Corporate Applications Engineer, Synopsys Learn how to predictably achieve high performance while minimizing power. We will present an optimized implementation methodology for an ARM Cortex™-A15 processor core based on Synopsys’ Galaxy™ Implementation platform. This session will highlight the latest technologies/techniques in Design Compiler and IC Compiler used to achieve challenging performance/power targets. These include physical guidance, delay performance vs. area tradeoffs, leakage optimization, innovative methods to reduce slack across register stages during final timing closure, and more. We will examine benefit/cost tradeoffs of each technique; performance/ease of convergence and impact on schedule/turnaround time. We will also share results obtained using this combination of optimized methodology, tools and physical IP. Key Takeaways: Cortex A-15 processor core optimization

Wednesday, October 26, 2011
	NXP Microcontroller Tools Workshop – Development Made Easy! Time: 10:00am - 12:00pm Location: Ballroom F Speakers: Amit Bhojraj, Product Marketing Manager, NXP Developing with NXP’s ARM-based microcontrollers has never been easier! This practical hands-on session will introduce attendees to the low cost development tool ecosystem provided by NXP and our tool partners, Code Red and ARM mbed. During the session, attendees will test NXP’s LPCXpresso IDE, the latest ARM mbed offering, and CodeRed’s new state machine development tool (RedState). All participants will receive a FREE NXP development tool.
	Kinetis ARM Cortex-M4 MCUs - This Kid’s Got Potential! Time: 10:45am - 11:35am Location: Ballroom G Speakers: Kevin McCann / Paulo Knirsch, Product Marketer, Industrial & Multi-Market, Microcontrollers Solutions Group, Freescale A ring-side view of the hottest contender on the embedded circuit. Equipped with speed (up to 150MHz), reach (up to 1MB Flash), and a killer blend of mixed-signal, connectivity, HMI, and security tricks up its sleeve, Kinetis is one MCU that punches above its weight class. This 50-minute work-out will cover the product families, software enablement and how you can get your hands on them before your competition does. Key Takeaways: An understanding of Kinetis products, tools, and how to take advantage.
	Synopsys Session 2: Performance Analysis of ARM CoreLink NIC-301 based Systems Using Synopsys Platform Architect Time: 11:00am - 11:50am Location: Ballroom H Speaker: Anthony Fama, Corporate Applications Engineer, Synopsys Learn how to efficiently explore and optimize the dynamic system performance of next-generation AMBA-based SoC designs in SystemC using a Smartbook case study example. During assembly, you'll see how to configure the initial parameters of the SBL-301 interconnect model using the Platform Architect flow with AMBA Designer. During simulation and analysis, you'll see how to define traffic scenarios and model parameters to explore architectures in Platform Architect, sweep through multiple simulations, and graphically analyze the root cause of performance problems. During exploration, you'll see how information is easily shared with spreadsheet tools for sensitivity analysis and how the optimal balance of performance, cost, and power is achieved in Platform Architect. Key Takeaways: System performance optimzation of AMBA-based SoC designs
	i.MX ARM Cortex-A9 MPUs--i.MX 6 Series: Breaking the Boundaries of User Experience Time: 11:45am - 12:35pm Location: Ballroom G Speaker: Kyle Fox, Product Marketing Manager, Multimedia Applications Division, Freescale Listen up, developers! Come experience a multimedia mecca and see for yourself why the i.MX 6 Series has been designated as the industry’s most scalable and powerful platform for multimedia and display applications. With best-in-class performance and a scalable product line, learn how our single, dual and quad core devices drive cutting-edge technologies such as 3D and augmented reality. Key Takeaways: An overview of our first multicore i.MX applications processor family.
	Ubuntu Core Time: 12:00pm - 12:50pm Location: Ballroom H Speaker: Lars Anderson, Business Development Manager, Canonical Introducing Ubuntu Core and How to get involved Ubuntu Core is a sub-set of Ubuntu technologies ideally suited for the next generation of embedded devices where Internet connectivity is key. It takes advantage of the extensive hardware, architecture and component certification work done by Canonical so manufacturers can build great experiences for non-PC-based technologies such as set-top boxes,in-vehicle infotainment systems and digital devices for the home. Key Takeaways: Work with Canonical and embed Ubuntu Core.
	NXP Cortex-M4 LPC4300 - When to Choose Cortex-M4 and Why Dual-Core? Time: 1:00pm - 2:00pm Location: Ballroom F Speaker: Gordon Cooper, Product Marketing Manager, NXP Shorten your high-performance microcontroller selection process by understanding the performance trade-offs between an ARM® Cortex™-M3, ARM® Cortex™-M4 and NXP’s asymmetrical dual-core LPC4300 digital signal controller. Learn the answers to the questions: Can the Cortex-M4 really replace a Digital Signal Processor? When would I choose a Cortex-M3? Is dual-core as complicated as it sounds? This session will provide practical advice and comparisons with benchmarks on these topics as well as a sneak peek into what’s to come. All participants will receive a FREE NXP development tool.
	Embedded Software Store Presentation and Lunch – hosted by ARM and Avnet Electronics Time: 1:00pm - 2:15pm Location: Mission Ballroom 5 The Embedded Software Store is an online information- and e-Commerce-based website delivering a marketplace whereby embedded designers can easily evaluate, access and purchase software supporting the ARM architecture. The site features a broad array of software options from ARM and Avnet’s extensive eco-system of partners. Additional features include a quick download delivery system, preview of all license agreements in advance of purchase and an online community providing a strong ecosystem of software support for hardware IP technology. This one stop online store enables easy access to a broad range of software accelerating your SoC design cycle.
	Kinetis ARM Cortex-M4 MCUs - Gloves Off - Hands-On! Time: 1:20pm - 3:40pm Location: Ballroom G Speakers: Melissa Hunter, Applications Engineer, Freescale; Anthony Huereca, Industrial & Multi-Market, Microcontrollers Solutions Group, Freescale Get in the ring with the ARM Cortex-M4, FlexMemory, Ethernet and a free $95,000 Real Time Operating System! This hands-on session will give you a feel for the power of Kinetis and the range of Freescale tools that support it - CodeWarrior IDE, MQX RTOS and the modular Tower Development System. Includes a demonstration of the K70 family with floating point unit, graphics LCD and tamper detect features, as well as the Graphics LCD, Sensing, and WiFi Tower development boards. Key Takeaways: An in-depth understanding of the Kinetis K60 family, CodeWarrior IDE, MQX RTOS and Tower Development System; and a demonstration of the new K70 with FPU.
	Get the Most Performance Out of Your Cortex-M4 Time: 2:15pm - 3:15pm Location: Ballroom F Speaker: Kenneth Dwyer, Applications Engineering Manager, NXP Want to get the most performance out of a Cortex-M4 microcontroller at a low system cost? Learn how to take advantage of the SPI Flash Interface (SPIFI) to cost-effectively add large amounts of Flash to your system on NXP’s dual-core LPC4300 with Cortex-M4 and Cortex-M0. We’ll explain how a simple Inter Processor Communication (IPC) software module on the LPC4300 unlocks the performance of the two 32-bit ARM cores. Attendees will see practical examples and demonstrations of these two unique peripherals. All participants will receive a FREE NXP development tool.
	Synopsys Session 3: Applying Virtual Prototyping to ARM-based Devices for Faster Software and Systems Development Time: 2:30pm - 3:20pm Location: Ballroom H Speaker: Marc Serughetti, Product Marketing Director, Synopsys As developers of ARM-based devices look for ways to accelerate time-to-market, reduce development costs and increase quality, they are increasingly turning towards virtual prototyping. In this session Synopsys will illustrate how virtual prototypes enable companies to jump start the development of software and systems based on an example from a leading semiconductor company. We will cover the benefits of virtual prototyping and its application to specific design tasks use with an emerging category of new devices. Key Takeaways: Accelerate software and systems development with virtual prototyping.
	ARM-based Processors in Networking: Runtime Software for Heterogeneous Multicore Time: 2:30pm - 3:20pm Location: Ballroom C Speaker: Conny Öhult, Director of Product Management, ENEA To achieve the highest level of system integration and performance, next generation systems for wireless basestations, small cells, gateways and many other networking applications will be built using a heterogeneous combination of ARM processors, DSPs and hardware accelerators. Developers adopting these devices will face a new level of complexity on the software level. In this presentation we will look into what the developer will need to overcome the performance, scalability and ease-of-use issues when adopting these new ARM based devices. Enea's platform for heterogeneous SoC include Linux, RTOS, Hypervisor, Interprocess Communication technology and the middleware and development tools needed to tie the entire software platform together, all designed to enable maximum design flexibility, late system partitioning, application transparency and seamless development and debug experience. Key Takeaways: Overcoming challenges of using ARM in Networking The advantage of using a single programming model on all systems processing nodes in a complex system
	Verifying Your ACE-Based SoC: Will Tried and True Methods Hold Up? Time: 3:30pm - 4:20pm Location: Ballroom H Speaker: Mirit Fromovich, Verification IP Solutions Architect, Cadence Design Systems; Paul Martin, Design Enablement & Alliances Manager, Cadence Design Systems Verifying cache coherent SOCs/systems employing ARM’s new AMBA® 4 ACE protocol is challenging since only up to date data may be used. It’s not sufficient for engineers to simply read the ACE specification -- they need specialized verification tools for ACE-based designs. But not just any VIP will do. Verifying ACE coherency is well beyond the ability of directed testing, the basic scheme most designers employ. To verify system level coherence requires two key capabilities: (1) constrained random stimulus generation capability; and (2) an interconnect monitoring solution. Key Takeaways: Learn the full range of cache coherency issues faced when verifying an SoC. How to define verification strategy and create testing scenarios to deliver high quality end products. Directed testing is insufficient to cover the range of scenarios and checks needed to validate coherency. What to look for when selecting an ACE verification solution.
	Solve Your Design Roadblocks Using NXP’s Flexible Peripherals Time: 3:30pm - 4:30pm Location: Ballroom F Speaker: Rob Cosaro, Systems Applications and Architecture Manager, NXP This class will cover two of NXP’s most flexible peripherals: the State Configurable Timer (SCT) and the Serial GPIO (SGPIO). The SCT is a flexible pulse width modulator block that can be modified by the designer to meet the requirements of applications using a new state tool that configures the SCT graphically. The serial GPIO is a flexible parallel to serial streaming peripheral that can be applied to custom user applications or extend the capabilities of the microcontroller. This session will provide a detailed understanding of the SCT and SGPIO by providing multiple application examples to clearly illustrate the power of these unique and flexible peripherals and how they can be used to solve designers’ biggest challenges. All participants will receive a FREE NXP development tool.
	i.MX ARM Cortex-A8 MPUs--Quick Bring Up on the i.MX53 Quick Start Board Time: 4:00pm - 6:20pm Location: Ballroom G Speakers: Dominic Selvaraj, Applications Engineering, Freescale; Marsha Chang, Product Marketing Manager, Multimedia Applications Division, Freescale Take your multimedia to the max. Experience first hand why developers are raving about the i.MX53 Quick Start Board, our first i.MX development system priced at less than $150. This hands-on session will cover a deep dive of the i.MX53 applications processor and guide you through bring up as well as a demo of the quick start board. Come see why the i.MX community is exploding around this full-featured, easy-to-use platform. Key Takeaways: Getting started with the easy-to-use i.MX53 Quick Start board.
	Simplify LCD-based Applications with Segger emWin and NXP Time: 4:45pm - 5:45pm Location: Ballroom F Speaker: Kevin Townsend, Applications Engineering Manager, NXP As development cycles and budgets get shorter and smaller, customer expectations for product interactivity and a good ‘user experience’ are on the rise. Developing or licensing a high-performance graphics libraries with modern features like anti-aliased text, clean charts and diagrams, and an efficient development work flow can be a significant challenge. With the new licensing agreement between NXP and Segger, users can now access cost-free and royalty-free use of Segger’s emWin library in any current NXP Cortex-M microcontroller. Learn how NXP and Segger make it possible to separate firmware and UI development in an efficient manner and how easy it is to include anti-aliased text and shapes, alpha-blending, windowing, and other advanced features in your next product. All participants will receive a FREE NXP development tool.

Thursday, October 27, 2011
	NXP Microcontroller Tools Workshop – Development Made Easy! Time: 10:00am - 12:00pm Location: Ballroom F Speakers: Amit Bhojraj, Product Marketing Manager, NXP Developing with NXP’s ARM-based microcontrollers has never been easier! This practical hands-on session will introduce attendees to the low cost development tool ecosystem provided by NXP and our tool partners, Code Red and ARM mbed. During the session, attendees will test NXP’s LPCXpresso IDE, the latest ARM mbed offering, and CodeRed’s new state machine development tool (RedState). All participants will receive a FREE NXP development tool.
	Keil Embedded Development and Serial Wire viewer debug with SmartFusion Time: 10:30am - 11:30am Location: Hands-On Lab Speaker: Tim McCarthy, Worldwide Training Manager, Microsemi Corporation This session will show how to use Keil development tools with a custom ARM cortex-M3 based SmartFusion device including how to debug using the Serial Wire Viewer. Key Takeaways: Three SmartFusion Evaluation Kits will be given away to attendees.
	Real-time Motor Control using SmartFusion customizable system-on-chip (cSoC) Time: 11:30am - 12:30pm Location: Hands-On Lab Speakers: Rufino Olay, Prasad Kuruganti, Product Marketing Managers, Microsemi Corporation FPGAs are increasingly being used in motor control applications due to their robustness and customizability. This demo will highlight the use of Microsemi's SmartFusion customizable system-on-chip (cSoC) implementing numerous motor/motion control algorithms including; Block Commutation with Hall Sensors & Field Oriented Control with Hall & Encorder using phase current measurements. Key Takeaways: Two Motor Control kits will be given away to attendees.
	Customize Your Own ARM-based System Time: 12:30am - 1:30pm Location: Hands-On Lab Speakers: Tim McCarthy, Worldwide Training Manager, Microsemi Corporation This session demonstrates how to customize Cortex-M3 based designs with additioanl peripherals in a device containing a hard ARM Cortex-M3 and complete microcontroller subsystem, a flash-based FPGA fabric and programmable analog in a single device. The session will cover architectural features and design flow with live demo. Key Takeaways: Three Smartfusion Evaluation Kits will be given out during the session.
	Get the Most Performance Out of Your Cortex-M4 Time: 1:00pm - 2:00pm Location: Ballroom F Speaker: Kenneth Dwyer, Applications Engineering Manager, NXP Want to get the most performance out of a Cortex-M4 microcontroller at a low system cost? Learn how to take advantage of the SPI Flash Interface (SPIFI) to cost-effectively add large amounts of Flash to your system on NXP’s dual-core LPC4300 with Cortex-M4 and Cortex-M0. We’ll explain how a simple Inter Processor Communication (IPC) software module on the LPC4300 unlocks the performance of the two 32-bit ARM cores. Attendees will see practical examples and demonstrations of these two unique peripherals. All participants will receive a FREE NXP development tool.
	EmCraft Systems presents uCLinux on SmartFusion with Display application Time: 1:30pm - 2:30pm Location: Hands-On Lab Speaker: Kent Meyer, EmCraft Systems This session will show how to run uClinux on SmartFusion devices and demonstrate a how to implement a low-cost graphical user interface solution running on the Microsemi SmartFusion customizable system-on-chip(cSoC) device using an SPI-connected LCD monitor. Key Takeaways: Two SmartFusion uClinux kits will be given away during the session.
	Solve Your Design Roadblocks Using NXP’s Flexible Peripherals Time: 2:15pm - 3:15pm Location: Ballroom F Speaker: Rob Cosaro, Systems Applications and Architecture Manager, NXP This class will cover two of NXP’s most flexible peripherals: the State Configurable Timer (SCT) and the Serial GPIO (SGPIO). The SCT is a flexible pulse width modulator block that can be modified by the designer to meet the requirements of applications using a new state tool that configures the SCT graphically. The serial GPIO is a flexible parallel to serial streaming peripheral that can be applied to custom user applications or extend the capabilities of the microcontroller. This session will provide a detailed understanding of the SCT and SGPIO by providing multiple application examples to clearly illustrate the power of these unique and flexible peripherals and how they can be used to solve designers’ biggest challenges. All participants will receive a FREE NXP development tool.
	Rapid USB Development on Cortex-M Microcontrollers Time: 3:30pm - 4:30pm Location: Ballroom F Speaker: Amit Bhojraj, Product Marketing Manager, NXP NXP offers the widest USB ARM® Cortex™-M based microcontroller portfolio with integrated high- and full-speed USB 2.0 device, host, and On-The-Go (OTG) technology. With support for all four endpoints including isochronous, EHCI/OHCI compliant host controllers, integrated FS and HS PHY and DMA interfaces, NXP has greatly enhanced the USB architecture bringing unparalleled design flexibility and reliable USB connectivity for consumer electronics and mobile devices. This session will show how rapid USB application development is made possible with USB class drivers from NXP that are built-in right into the chip, and introduce attendees to several low cost development boards and free software tools. Each attendee will walk away with a FREE LPCXpresso development kit.